A successive approximation analog-to-digital converter (ADC) has been the mainstay of data acquisition systems for many years. Recent design improvements have extended the sampling frequency of these ADCs into the megahertz region with 18-bit resolution. The basic successive approximation ADC performs conversions on command. In order to process AC signals, SAR ADCs must have an input sample-and-hold device to keep the signal constant during the conversion cycle. On the assertion of a CONVERT START command, the sample-and-hold device is placed in the hold mode, and an internal digital-to-analog converter (DAC) is set to mid-scale. A comparator determines whether the sampled analog value is above or below the DAC output, and the result (bit 1, the most significant bit of the conversion) is stored in the successive approximation register (SAR). The DAC is set either to ¼ scale or ¾ scale (depending on the value of bit 1), and the comparator makes the decision for bit 2 of the conversion. The result is stored in the register, and the process continues until all of the bit values have been determined. When all the bits have been set, tested, and reset or not as appropriate, the contents of the SAR correspond to the value of the analog input, and the conversion is complete. These bit “tests” form the basis of a serial output version SAR ADC. Note that the acronym “SAR” actually stands for Successive Approximation Register (the logic block that controls the conversion process), but is universally accepted as the acronym for the architecture itself.
The DAC portion of the SAR ADC can utilize a capacitor network. The advantage of the switched-capacitor DAC is that the accuracy and linearity is primarily determined by high-accuracy photolithography, which in turn controls the capacitor plate area, and the capacitance as well as matching. In addition, small capacitors can be placed in parallel with the main capacitors, which can be switched in and out with bit switches under control of autocorrelation routines to achieve high accuracy and linearity without the need for thin-film laser trimming.
Each of the capacitors in the switched capacitor DAC has one plate thereof connected to a common node, which is connected to one input of a comparator, and the other plate thereof connected to an associated switch that can connect the plate to ground, the analog input voltage, AIN, or a reference voltage, VREF. In the sample or tracking mode, the analog input voltage, AIN, is constantly charging and discharging the parallel combination of all the capacitors. The hold mode is initiated by opening the switch, thus leaving the sampled analog input voltage on the capacitor array. Typically, the other input of the comparator is connected to ground or a common mode voltage. Some type of auto-zero switch will maintain the inputs at the same voltage until after AIN has been sampled, at which time the common node is allowed to “float” allowing the voltage at the common node to move as the bit switches are manipulated. If respective bit switches are all connected to ground, a voltage equal to −AIN appears at the common node. Connecting the bit switch for the most significant bit (MSB) to VREF adds a voltage equal to VREF/2 to −AIN. The comparator makes the MSB bit decision, i.e., is the common node above the voltage on the reference input to the comparator, and the SAR either leaves MSB bit switch connected to VREF or connects it to ground depending on the comparator output (which is high or low depending on whether the voltage at the common node is negative or positive, respectively).
The various components of the SAR ADC require bias currents to operate. The bias current needs can be different based on the power requirements of the SAR ADC. There is a need to provide the ability to alter these bias currents based upon the power requirements of the SAR ADC.